A Pipelined Multi-core MIPS Machine
Hardware Implementation and Correctness Proof
Book Details:
| Publisher: | Springer |
| Series: | Springer , Implementation |
| Author: | Mikhail Kovalev |
| Edition: | 1 |
| ISBN-10: | 3319139053 |
| ISBN-13: | 9783319139050 |
| Pages: | 352 |
| Published: | Nov 27 2014 |
| Posted: | May 04 2015 |
| Language: | English |
| Book format: | |
| Book size: | 5.49 MB |
Book Description:
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.
Download Link:
Related Books:
Software Development for Embedded Multi-core Systems
A Practical Guide Using Embedded Intel Architecture
The multicore revolution has reached the deployment stage in embedded systems ranging from small ultramobile devices to large telecommunication servers. The transition from single to multicore processors, motivated by the need to increase performance while conserving power, has placed great responsibility on the shoulders of software engineers. In this new embedded multicore era, the toughest task is the development of code to support more sophisticated systems. This book provides embedded engineers with solid grounding in the skills required to develop software targeting multicore processors. Within the text, the author undertakes an in-depth exploration of performance analysis, and a close-up look at the tools of the trade. Both general multicore d...
Multi-Core Embedded Systems
Details a real-world product that applies a cutting-edge multi-core architecture Increasingly demanding modern applicationssuch as those used in telecommunications networking and real-time processing of audio, video, and multimedia streamsrequire multiple processors to achieve computational performance at the rate of a few giga-operations per second. This necessity for speed and manageable power consumption makes it likely that the next generation of embedded processing systems will include hundreds of cores, while being increasingly programmable, blending processors and configurable hardware in a power-efficient manner. Multi-Core Embedded Systems presents a variety of perspectives that elucidate the technical challenges associated with such increa...
Intel Threading Building Blocks
Outfitting C++ for Multi-core Processor Parallelism
Multi-core chips from Intel and AMD offer a dramatic boost in speed and responsiveness, and plenty of opportunities for multiprocessing on ordinary desktop computers. But they also present a challenge: More than ever, multithreading is a requirement for good performance. This guide explains how to maximize the benefits of these processors through a portable C++ library that works on Windows, Linux, Macintosh, and Unix systems. With it, you'll learn how to use Intel Threading Building Blocks (TBB) effectively for parallel programming -- without having to be a threading expert.Written by James Reinders, Chief Evangelist of Intel Software Products, and based on the experience of Intel's developers and customers, this book explains the key tasks in multi...
2007 - 2021 © eBooks-IT.org