Source-Synchronous Networks-On-Chip
Circuit and Architectural Interconnect Modeling
Book Details:
Publisher: | Springer |
Series: |
Springer
|
Author: | Ayan Mandal |
Edition: | 1 |
ISBN-10: | 1461494044 |
ISBN-13: | 9781461494041 |
Pages: | 160 |
Published: | Nov 27 2013 |
Posted: | Nov 19 2014 |
Language: | English |
Book format: | PDF |
Book size: | 2.59 MB |
Book Description:
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
This book addresses reliability and energy efficiency of on-chip networks using cooperative error control. It describes an efficient way to construct an adaptive error control codec capable of tracking noise conditions and adjusting the error correction strength at runtime. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance....
Describes in a consolidated way the results of a three-year research project, during which researchers from leading european industrial companies and research institutes have been working together. Contributors come from academia and industry, such companies as INTRACOM, VTT and Nokia being represented Proposes brand new approaches based on SystemC and OCAPI-XL that explicitly handle issues related to reconfiguration at the system level Introduces a design flow for designing reconfigurable systems-on-chip Provides a comprehensive introduction to reconfigurable hardware and existing reconfigurable technologies Presents examples on how reconfigurable hardware can be exploited for the development of complex systems Provides useful feedback from the appl...
This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors ...
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